Tytuł:

FPGA-based Low Latency Square Root CORDIC Algorithm, Journal of Telecommunications and Information Technology, 2025, nr 1

Tytuł publikacji grupowej:

2025, nr 1, JTIT-artykuły

Autor:

Węgrzyn, Mariusz ; Voytusik, Stepan ; Gavkalova, Nataliia

Temat i słowa kluczowe:

computer vision ; CORDIC algorithm ; FPGA ; numerical methods ; reconfigurable computing systems

Opis:

kwartalnik

Abstrakt:

The coordinate rotation digital computer (CORDIC) algorithm is a popular method used in many fields of science and technology. Unfortunately, it is a time-consuming process for central processing units (CPUs) and graphics processing units (GPUs), and even for specialized digital signal processing (DSP) solutions. The CORDIC algorithm is an alternative for Newton-Raphson numerical calculation and for the FPGA based resource-expensive look-up-table (LUT) method. Various modifications of the CORDIC algorithm allow to speed up the operation of hardware in edge computing devices. With that context taken into consideration, this article presents a fast and accurate square root floating point (SQRT FP) CORDIC function which can be implemented in field programmable gate arrays (FPGAs). The proposed algorithm offers low-complexity, decent accuracy and speed, and is sufficient for digital signal processing (DSP) applications, such as digital filters, accelerators for neural networks, machine learning and computer vision applications, and intelligent robotic systems.

Numer:

1

Wydawca:

National Institute of Telecommunications

Data wydania:

2025, nr 1

Typ zasobu:

artykuł

DOI:

10.26636/jtit.2025.1.1950

eISSN:

on-line: ISSN 1899-8852

Źródło:

Journal of Telecommunications and Information Technology

Język:

ang

Prawa:

Biblioteka Naukowa Instytutu Łączności

Licencja:

CC BY 4.0