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Title: Design Exploration of AES Accelerators on FPGAs and GPUs, Journal of Telecommunications and Information Technology, 2017, nr 1

Creator:

Vitabile, Salvatore ; Conti, Vincenzo

Date:

2017, nr 1

Resource Type:

artykuł

Description:

The embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems and an exhaustive analysis of the state of the art of all current performance with respect to architectures, design methodologies, test and applications could be very interesting. The Advanced Encryption Standard (AES), based on the well-known algorithm Rijndael, is designed to be easily implemented in hardware and software platforms. General purpose computing on graphics processing unit (GPGPU) is an alternative to recongurable accelerators based on FPGA devices. This paper presents a direct comparison between FPGA and GPU used as accelerators for the AES cipher. The results achieved on both platforms and their analysis has been compared to several others in order to establish which device is best at playing the role of hardware accelerator by each solution showing interesting considerations in terms of throughput, speedup factor, and resource usage. This analysis suggests that, while hardware design on FPGA remains the natural choice for consumer-product design, GPUs are nowadays the preferable choice for PC based accelerators, especially when the processing routines are highly parallelizable.

Publisher:

National Institute of Telecommunications

Format:

application/pdf

Resource Identifier:

ISSN 1509-4553, on-line: ISSN 1899-8852 ; oai:bc.itl.waw.pl:1965

Source:

Journal of Telecommunications and Information Technology

Language:

ang

Rights Management:

Biblioteka Naukowa Instytutu Łączności

Subject and keywords:

AES GPGPU FPGA prototyping GPGPU OpenCL OpenCL accelerators

Object collections:

Last modified:

May 11, 2017

In our library since:

May 11, 2017

Number of object content hits:

234

All available object's versions:

https://ribes-54.man.poznan.pl/publication/2242

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Edition name Date
Conti, Vincenzo, 2017, nr 1, Design Exploration of AES Accelerators on FPGAs and GPUs, Journal of Telecommunications and Information Technology, 2017, nr 1 May 11, 2017

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